Radiation Hardened and High Temperature EEPROMS

EEPROMs

Northrop Grumman offers the only Radiation Hardened EEPROMs with the ability to re-write to memory.

The radiation hardened robustness of the design (performed by Sandia National Laboratories) and fabrication process is flight proven with more than 10,000 radiation hardened EEPROM devices previously delivered to production systems. This product line offers the only solid-state reprogrammable nonvolatile memory available today that is inherently radiation hardened. No special shielding, specialized packages, redundant devices, or special power down is required to operate these devices in severe radiation environments. Users have the ability to re-write to memory more than 10,000 times with retention of 10 years.

Please contact us at Ask-MSTC@ngc.com for more information.

Our high temperature EEPROMs

Our radiation hardened EEPROMs

  • 1MB Radiation Hardened CMOS EEPROM
    The W28C0108 radiation hardened nonvolatile 1Mbit (128K x 8) EEPROM is intended for use in space and harsh radiation environments where critical system data (Program Store, Start Up Read Only Memory, etc.) cannot be compromised during radiation exposure, or lost during power outages.

  • 256k Radiation Hardened CMOS EEPROM
    The W28C256 is a 32K x 8 radiation hardened EEPROM designed by Sandia National Laboratories, Albuquerque, NM, and manufactured by the Northrop Grumman Advanced Technology Center, Baltimore, MD, using nonvolatile memory technology transferred from Sandia. It is built using a mature dual well CMOS process using N on N+ epitaxial silicon and a two layer interconnect system. Read the conference paper: A 256 kb (32kx8) EEPROM for >200 °C Applications.

  • 64k Radiation Hardened CMOS EEPROM
    The W28C64 is a 8K x 8 radiation hardened EEPROM designed by Sandia National Laboratories, Albuquerque, NM, and manufactured by Northrop Grumman Advanced Technology Center, Baltimore, MD, using nonvolatile memory technology transferred from Sandia. It is built using a mature dual well CMOS process using N on N+ epitaxial silicon and a two layer interconnect system.

Features include:

  • 0.8 / 1.25 / 1.25 µm Rad Hardened CMOS on EPI
  • Total Dose up to 300 kRads (Si)
  • Memory Data Loss > 1E12 Rad(Si)/sec
  • Single Event Upset in Address/Data Latches During Read LETth = 35 MeV/mg/cm²
  • No Latchup
  • JEDEC pin compatible in center 32p LCC
  • Self Timed Programming
  • Auto Program Start
  • Asynchronous Addressing
  • Address access time < 200 µsec
  • Transient Logic Upset > 5E7 Rad(Si)/sec
  • Single Event Upset During READ LETth = 60 MeV/mg/cm²
  • Permanent SEU Damage (During Write Only) greater than or equal to Kr
  • Compatible with Commercial EEPROMs
  • Full military operating temperature range, screened to specific test methods for commercial, Class B, or modified Hi Rel
  • Combined Erase/Write
  • +3.3V / +5V / +5V only read operation
  • 128 / 64 / 64 Word page
  • Data Polling