Staff Digital Engineer (FPGA or ASIC Design)

Northrop Grumman Mission Systems Sector (NGMS) is a leading global provider of secure software-defined, hardware enabled mission systems. Our company is pioneering capabilities in a wide variety of sectors that keep our nation and our allies safe from undersea to space and cyberspace. NGMS is seeking a Staff Engineer with the desire to learn new technologies to join our innovative Digital Technologies Organization to help develop, enhance and maintain FPGA and/or ASIC designs on cutting edge products and systems. As a Staff Digital Engineer at Northrop Grumman you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformation. Through the use of Model-based Engineering, DevSecOps and Agile practices we continue to evolve how we deliver critical national defense products and capabilities for the warfighter. Our success is grounded in our ability to embrace change, move quickly and continuously drive innovation. The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In this capacity, you will utilize your working knowledge of digital signal processing and digital interfaces.

This position is located in Linthicum, MD or Morrisville, NC.

Basic Qualifications:

• Education and Years of Experience
  • BS degree and 14+ years of digital design experience, or
  • MS degree and 12+ years of digital design experience, or
  • PhD and 9+ years of digital design experience, or
  • An additional 4 years of experience can be used in lieu of a BS degree

• US Citizenship is required
• Working knowledge of full product life cycle (requirements, design, implementation and test) of FPGA Design and/or ASIC Design
• Knowledge of System Verilog, Verilog and/or VHDL
• An active DoD Secret Security Clearance is required

Preferred Qualifications:

• Advanced Degrees in Electrical Engineering or comparable engineering discipline
• Experience with industry standard FPGA design implementation tools for IP integration, PnR, CDC such as Xilinx Vivado, Intel Quartus, and QuestaSim.
• Experience with industry standard ASIC front-end design tools for synthesis, LEC, CDC
• Experience with STA constraints generation and timing closure
• Experience with MATLAB, Mentor Graphics design tools, Synopsys or similar tool
• Familiarity with Xilinx and Intel FPGA technology

This position is contingent upon transfer of DoD Secret Clearance and Special Program Access (SAP) prior to starting. 

The health and safety of our employees and their families is a top priority. The company encourages employees to remain up-to-date on their COVID-19 vaccinations. U.S. Northrop Grumman employees may be required, in the future, to be vaccinated or have an approved disability/medical or religious accommodation, pursuant to future court decisions and/or government action on the currently stayed federal contractor vaccine mandate under Executive Order 14042 https://www.saferfederalworkforce.gov/contractors/.

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.