iReturn - Principal Digital ASIC Circuit Design Engineer/ Sr. Principal Digital ASIC Circuit Design Engineer

At Northrop Grumman Mission Systems we understand that sometimes we must pause our professional life to support our family and loved ones. After taking a career break to care for children, aging parents or other family obligations, the road to return to work can be intimidating. iReturn can be the steppingstone in returning to your career.

We are seeking experienced and motivated professionals who are looking to return to the workforce after a career break of a minimum of 2 years .

Responsibilities:

• Circuit behavioral coding in Verilog, System Verilog or VHDL RTL.
• Circuit synthesis, formal verification, and static timing using state of the art digital ASIC design tools.
• Developing verification plans based on requirements of the circuit and creating circuit functional test benches in RTL.
• Generating manufacturing test vectors and manufacturing circuit test plan
• Help to develop automated procedures to streamline digital design procedures.

This position requires onsite work at our Advanced Technology Lab in Linthicum, MD.

This position can be filled at the Principal level OR the Sr. Principal level. Qualifications for both are listed below:

Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:

• A career break of at least 2 years
• Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with technical MS and 0 years with Ph.D.).
• Experience with full product life cycle (requirements, design, implementation, test) of ASIC design.
• Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion).
• Proficiency with current ASIC design tools for all phases described below: Simulation – Mentor ModelSim, Cadence Excelium, Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus.
• U.S. Citizenship with the ability to obtain and maintain US Security Clearance.

Basic Qualifications for Sr. Principal Digital ASIC Circuit Design Engineer Level:

• A career break of at least 2 years
• Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 9 years of relevant experience (7 years with technical MS, 4 years with technical PhD).
• Experience with full product life cycle (requirements, design, implementation, test) of ASIC design.
• Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion).
• Proficiency with current ASIC design tools for all phases described below: Simulation – Mentor ModelSim, Cadence Excelium Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL. Compiler - Static Timing – Synopsys Primetime or Cadence Tempus.
• U.S. Citizenship with the ability to obtain and maintain US Security Clearance.

Preferred Qualifications:

• Advanced Degree - either MS or PhD.
• Current security clearance or eligibility.
• Experience with chip level integration and ASIC chip lead - Strong design automation skills.
• Experience in CAD design network, tool configuration, and data management.
• Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre Familiarity with revision control and EDA standard formats used in cell/library development and modeling – Liberty (timing model), SDC (Synopsys Design Constraints).
• Active DoD Top Secret Clearance.

NGiReturn