Principal / Senior Principal Circuit Design Engineer / Layout Engineer

The Northrop Grumman Mission Systems (NGMS) Advanced Processing Solutions (APS) Business pushes the boundaries of innovation, redefines the leading edge of exotic new technologies, and drives advances in the sciences. One of our most challenging new fields is Transformational Computing, which combines the unique properties of superconductivity and quantum mechanics to develop radical new energy-efficient computing systems. Our team is chartered with providing the skills to transform computing beyond Moore’s Law, advancing development of computer architectures, processing/memory subsystems, and large-scale high-performance computing systems. You’ll work in a fast-paced team environment alongside a broad array of scientists, engineers and physicists to make these processing solutions a reality and deliver remarkable new advantages to the warfighter.

The Networked Information Solutions (NIS) Advanced Processing Solutions (APS) business is seeking a Principal / Senior Principal Circuit Design Engineer / Layout Engineer.  The ideal candidate will have solid understanding of microelectronic electrical principles, demonstrated organizational skills and a willingness to learn and grow in a team environment.  The development nature of our foundry activities will provide a willing candidate the opportunity to grow into an integral member of the Northrop Grumman design community.

Responsibilities (including, but not limited to):

• Create custom designs and layouts that could include Process Control Monitor (PCM) structures, reticle alignment marks, and physical measurement structures. Mentoring and guidance are provided by process engineers, photo lithography engineers and peer engineers.
• Provide floor planning guidance and support.
• Create chip designs in various technologies for process prove-in, experimentation, and test support.
• Perform both frontend and backend verification of designs.
• Participate in reticle composition and tape out activities.
• Document work performed.

Additional Valuable Skills:

• Experience using Cadence design suite of tools to perform full and semi-custom design work.
  • Knowledge of Cadence Virtuoso L/XL/EXL capabilities that enhance design task efficiency.
• Knowledge of semiconductor device physics and analog/mixed signal integrated circuit design.
• Experience laying out or characterizing digital standard cells or memory elements.
• Design simulation using industry tools such as ANSYS/HFSS or ADS.
• Building scripts, in an agreed upon programing language, to automate repetitive tasks or facilitate an increase in productive work.
• Create and document flows for future re-use and quality control.
• Knowledge of an industry programing language: Shell, Python, Perl, TCL/TK or equivalent.
• Experience with any of the following:
  • Behavior modeling skills using Verilog-A or Verilog-AMS.
  • Full-chip functional/performance verification methods.
• Experience collaborating with research staff/quantum physicists to realize proof of principle designs.

This position requires onsite support at our Advanced Technology Lab (ATL) in our Linthicum, MD office.

This position can be filled as a Principal Circuit Design Engineer / Physical Layout Design Engineer OR a Senior Principal Circuit Design Engineer / Physical Layout Design Engineer. Qualifications for both are listed below:
 

Basic Qualifications for a Principal Circuit Design Engineer / Physical Layout Design Engineer:

• Bachelor’s Degree in a STEM related field with 5 years of related experience; 3 years with Masters; 0 years with PhD.
• Excellent verbal, written, and interpersonal communication skills.
• Navigate file structures in the LINUX environment.
• Able to obtain and maintain a DoD security clearance per business requirements.
• US Citizenship.

Basic Qualifications for a Senior Principal Circuit Design Engineer / Principal Physical Layout Design Engineer:

• Bachelor’s Degree in a STEM related field with 9 years of related experience; 7 years with Masters; 4 with a PhD.
• Excellent verbal, written, and interpersonal communication skills.
• Navigate file structures in the LINUX environment.
• Able to obtain and maintain a DoD security clearance per business requirements.
• US Citizenship.

Preferred Qualifications for Principal Circuit Design Engineer / Physical Layout Design Engineer OR Senior Principal Circuit Design Engineer / Principal Physical Layout Design Engineer:

• Understanding of the Semiconductor fabrication process and process development.
• Understanding of Process Design Kit (PDK) Development (tech files, verification rule files, Pcells, skill programing)
• Skilled in the use of the Cadence Virtuoso capture tool.
• Proficient in the use of Cadence ASSURA or Siemens Mentor Calibre DRC/LVS verification tools.
• Experience in Superconducting Reciprocal Quantum Logic circuit design practices
• Current Secret/TS SCI clearance

The health and safety of our employees and their families is a top priority. The company encourages employees to remain up-to-date on their COVID-19 vaccinations. U.S. Northrop Grumman employees may be required, in the future, to be vaccinated or have an approved disability/medical or religious accommodation, pursuant to future court decisions and/or government action on the currently stayed federal contractor vaccine mandate under Executive Order 14042 https://www.saferfederalworkforce.gov/contractors/.

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.