Principal or Senior Principal Circuit Design Engineer / Layout Engineer
Requisition ID: R10172236
- Category: Engineering
- Location: Linthicum, Maryland, United States of America | Annapolis Junction, Maryland, United States of America+ 1 more
- Clearance Type: Polygraph
- Telecommute: No- Teleworking not available for this position
- Shift: 1st Shift (United States of America)
- Travel Required: Yes, 10% of the Time
- Relocation Assistance: Relocation assistance may be available
- Positions Available: 1
The Northrop Grumman Mission Systems (NGMS) Advanced Processing Solutions (APS) Business pushes the boundaries of innovation, redefines the leading edge of exotic new technologies, and drives advances in the sciences. One of our most challenging new fields is Transformational Computing, which combines the unique properties of superconductivity and quantum mechanics to develop radical new energy-efficient computing systems. Our team is chartered with providing the skills to transform computing beyond Moore’s Law, advancing development of computer architectures, processing/memory subsystems, and large-scale high-performance computing systems. You’ll work in a fast-paced team environment alongside a broad array of scientists, engineers and physicists to make these processing solutions a reality and deliver remarkable new advantages to the warfighter.
The Networked Information Solutions (NIS) Advanced Processing Solutions (APS) business is seeking a Principal or Senior Principal Circuit Design Engineer / Layout Engineer. The ideal candidate will have solid understanding of microelectronic electrical principles, demonstrated organizational skills and a willingness to learn and grow in a team environment. The development nature of our foundry activities will provide a willing candidate the opportunity to grow into an integral member of the Northrop Grumman design community.
Responsibilities (including, but not limited to):
Create custom designs and layouts that could include Process Control Monitor (PCM) structures, reticle alignment marks, and physical measurement structures. Mentoring and guidance are provided by process engineers, photo lithography engineers and peer engineers.
Provide floor planning guidance and support.
Create chip designs in various technologies for process prove-in, experimentation, and test support.
Perform both frontend and backend verification of designs.
Participate in reticle composition and tape out activities.
Document work performed.
Additional Valuable Skills:
Experience using Cadence design suite of tools to perform full and semi-custom design work.
Knowledge of Cadence Virtuoso L/XL/EXL capabilities that enhance design task efficiency.
Knowledge of semiconductor device physics and analog/mixed signal integrated circuit design.
Experience laying out or characterizing digital standard cells or memory elements.
Design simulation using industry tools such as ANSYS/HFSS or ADS.
Building scripts, in an agreed upon programing language, to automate repetitive tasks or facilitate an increase in productive work.
Create and document flows for future re-use and quality control.
Knowledge of an industry programing language: Shell, Python, Perl, TCL/TK or equivalent.
Experience with any of the following:
Behavior modeling skills using Verilog-A or Verilog-AMS.
Full-chip functional/performance verification methods.
Experience collaborating with research staff/quantum physicists to realize proof of principle designs.
This position requires onsite support at our Linthicum, MD or Annapolis Junction, MD campuses.
This position can be filled as a Principal Circuit Design Engineer / Layout Design Engineer OR a Senior Principal Circuit Design Engineer / Layout Design Engineer.
Basic Qualifications for a Principal Circuit Design Engineer / Layout Design Engineer:
Bachelor’s Degree in a STEM related field with 5 years of related experience; 3 years with Masters; 0 years with PhD. An additional 4 year's experience in lieu of degree will be considered.
Excellent verbal, written, and interpersonal communication skills.
Navigate file structures in the LINUX environment.
US Citizen with ability to obtain and maintain a TS/SCI with polygraph security clearance.
Basic Qualifications for a Senior Principal Circuit Design Engineer / Layout Design Engineer:
Bachelor’s Degree in a STEM related field with 8 years of related experience; 6 years with Masters; 4 with a PhD. An additional 4 year's experience in lieu of degree will be considered.
Excellent verbal, written, and interpersonal communication skills.
Navigate file structures in the LINUX environment.
US Citizen with ability to obtain and maintain a TS/SCI with polygraph security clearance.
Preferred Qualifications:
Understanding of the Semiconductor fabrication process and process development.
Understanding of Process Design Kit (PDK) Development (tech files, verification rule files, Pcells, skill programing)
Skilled in the use of the Cadence Virtuoso capture tool.
Proficient in the use of Cadence ASSURA or Siemens Mentor Calibre DRC/LVS verification tools.
Experience in Superconducting Reciprocal Quantum Logic circuit design practices
Current Secret/TS SCI clearance
#NGMCENG
Employees may be eligible for a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.
Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.
What's great about
Northrop Grumman
- Be part of a culture that thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work.
- Use your skills to build and deliver innovative tech solutions that protect the world and shape a better future.
- Enjoy benefits like work-life balance, education assistance and paid time off.
Did you know?
Northrop Grumman leads the industry team for NASA’s James Webb Space Telescope, the largest, most complex and powerful space telescope ever built. Launched in December 2021, the telescope incorporates innovative design, advanced technology, and groundbreaking engineering, and will fundamentally alter our understanding of the universe.