Principal Digital Engineer / Senior Principal Digital Engineer

Northrop Grumman Mission Systems is seeking a Digital Engineer to develop, enhance and maintain software on cutting edge products and systems. The Digital Engineer will work on software systems for mission systems in all phases of the software development lifecycle, primarily in FPGA.

This requisition may be filled as a Principal Digital Engineer or Senior Principal Digital Engineer and will be located in Baltimore, MD or Linthicum, MD.

Basic Qualifications for a Principal Digital Engineer:

• Bachelor’s degree with 5 years of experience, a Master’s degree with 3 years of experience or a PhD with 0 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields; will consider 4 years of applied experience in lieu of degree requirement.

• U.S Citizenship is required

• A final DoD Secret clearance is required to start.

• Working knowledge of full product life cycle (requirements, design, implementation and test) of FPGA Design and/or ASIC Design

• Knowledge of System Verilog, Verilog and/or VHDL

Basic Qualifications for a Senior Principal Digital Engineer:

• Bachelor’s degree with 9 years of experience, a Master’s degree with 7 years of experience or a PhD with 4 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields; will consider 4 years of applied experience in lieu of degree requirement.

• U.S Citizenship is required

• A final DoD Secret clearance is required to start.

• Working knowledge of full product life cycle (requirements, design, implementation and test) of FPGA Design and/or ASIC Design

• Knowledge of System Verilog, Verilog and/or VHDL

Preferred Qualifications:

• Advanced Degrees in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields

• Active DoD Secret Clearance or higher

• Experience with industry standard FPGA design implementation tools for IP integration, PnR, CDC such as Xilinx Vivado, Intel Quartus, and QuestaSim.

• Experience with industry standard ASIC front-end design tools for synthesis, LEC, CDC

• Experience with STA constraints generation and timing closure

• Experience with MATLAB, Mentor Graphics design tools, Synopsys or similar tool

• Familiarity with Xilinx and Intel FPGA technology

• U.S Citizenship with the ability to obtain/maintain an active DoD Secret Clearance

This position is contingent upon the ability to obtain / maintain an active DoD Secret Clearance prior to starting. 

The health and safety of our employees and their families is a top priority. The company encourages employees to remain up-to-date on their COVID-19 vaccinations. U.S. Northrop Grumman employees may be required, in the future, to be vaccinated or have an approved disability/medical or religious accommodation, pursuant to future court decisions and/or government action on the currently stayed federal contractor vaccine mandate under Executive Order 14042 https://www.saferfederalworkforce.gov/contractors/.

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.